This application is based upon and claims priority from prior French Patent Application No. 0103469, filed Mar. 14, 2001, the disclosure of which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The invention relates to semiconductor components, especially those intended to be integrated into high-frequency technologies with a very high degree of integration (VLSI technology: xe2x80x9cVery Large Scale Integrationxe2x80x9d), and especially bipolar transistors of the double-polysilicon, self-aligned, silicon/germanium heterojunction-base type, in particular those having an epitaxially grown base, and their method of manufacture.
2. Description of Related Art
A double-polysilicon transistor is formed with both the emitter and the extrinsic base made of polycrystalline silicon (polysilicon). In contrast a single-polysilicon bipolar transistor is formed with only the emitter made of polysilicon.
Furthermore, a double-polysilicon transistor is said to be xe2x80x9cself-alignedxe2x80x9d when the distance between the polysilicon of the extrinsic base and the polysilicon of the emitter is not defined by any photolithography operation, stated differently, by any adjustment of two photolithography masks with respect to one another.
A conventional method of fabricating a self-aligned double-polysilicon bipolar transistor, in which the intrinsic base is implanted, is to deposit a stack of layers. This stack is deposited on an active area of a semiconducting substrate, having a given type of conductivity (for example N type). The stack of layers includes a layer of polysilicon heavily doped with a type of conductivity opposite to that of the substrate (for example P+ doped) surmounted by an upper insulating layer, for example of silicon dioxide. The P+ polysilicon layer is intended to form the extrinsic base of the transistor later. Next, the stack is etched above the active area so as to define an emitter window. Electrical-insulation regions or xe2x80x9cspacersxe2x80x9d are produced on the side faces of the emitter window and polysilicon is deposited in the emitter window in such a way as to form the emitter region. This emitter region is thus insulated from the extrinsic base by the internal spacers and also by a part of the upper insulating region of the stack on which this emitter region partially rests.
During the operation of etching of the stack, a problem of over-etching occurs which has the effect of removing some of the silicon from the active area. The control and the reproducibility of this over-etching are sufficient in the context of an implanted-base transistor, in which the implantation of the intrinsic base is generally carried out after the opening of the emitter window.
The problem of over-etching is different in a transistor with an epitaxially grown base, in particular if it is desired to have available an intrinsic base with silicon/germanium heterojunction. This is because, in transistors with an epitaxially grown base, non-selective epitaxy is generally used to deposit on the active area, and on the insulating regions delimiting this active area, a semiconducting region within which the future intrinsic base will be produced. The stack of layers set out above is then deposited on this first semiconducting region. However, the thickness of the first semiconducting region, that is to say the thickness of the intrinsic base, is particularly small, typically a few tens of nanometers. And this intrinsic base, already particularly thin at the outset, is inevitably partially etched as a result of the over-etching the stack when the emitter window is defined. This can lead to degradations in the electrical functioning of the transistor, or even to a defective transistor.
One solution to overcome this problem of over-etching consists of carrying out the epitaxial growth of the intrinsic base only after the emitter window has been etched. However, such a solution requires the use of selective epitaxy, which poses other, more intricate technological problems than for non-selective epitaxy, such as more intricate control of the thickness of the base, as well as greater difficulties in obtaining a high quality of the epitaxially grown base. Accordingly, a need exists to overcome this problem of over-etching in a transistor with an epitaxially grown base.
The present invention is a method to produce a transistor of the double-polysilicon, heterojunction-base type, which uses non-selective epitaxy of the base while remaining simple to fabricate and with good performance.
The method of fabricating a bipolar transistor of the double-polysilicon, heterojunction-base type, according to one aspect of the invention, comprises the following stages:
a semiconducting layer with silicon/germanium heterojunction is formed by non-selective epitaxy on an active region of a semiconducting substrate and an insulating region surrounding the active region;
at least one etching stop layer is formed on the heterojunction semiconducting layer above a part of the active region;
a layer of polysilicon and an upper insulating layer can be on the heterojunction semiconducting layer and on a part of the stop layer, in such a way that an emitter window is left free; and
an emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the heterojunction semiconducting layer. Spacers are advantageously formed in the emitter window.
The active region of the substrate can be prepared beforehand by ion implantation in order to form n+ type and p+ type buried layers, an epitaxially grown collector of n type, and an insulating region.
In one embodiment of the invention, it is possible to form a lower insulating layer, beforehand, covering the active region and the insulating region surrounding the active region, and to etch the insulating layer in order to define an aperture above the active region and a part of the insulating region surrounding the active region. The insulating layer may comprise silicon oxide, silicon oxynitride and/or amorphous silicon.
In another embodiment of the invention, the silicon/germanium heterojunction semiconducting layer is formed in the aperture directly on the active region.
In still another embodiment of the invention, a lower stop layer and an upper stop layer are formed with compositions such that they can be etched selectively. The lower stop layer may includes silicon oxide and the upper stop layer includes silicon nitride. The stop layers are formed by deposition then etching. The upper surface of the heterojunction semiconducting layer is cleaned in order to remove from it any traces of oxide, for example with hydrofluoric acid.
In yet still another embodiment of the invention, the polysilicon layer is deposited non-selectively, then is doped in order to form p+ type conductivity on it, then the upper insulating layer is deposited non-selectively, then the upper insulating layer and the polysilicon layer are etched selectively above a part of the etching stop layer, the etching being stopped substantially on the etching stop layer. The polysilicon layer is doped with boron. The upper insulating layer is silicon oxide. Etching, such as anisotropic etching, is performed. It is then possible to dope a part of the active region by an N type species such as phosphorus or arsenic which will pass through the etching stop layer or layers.
The spacers are formed by deposition of an insulating material in the emitter window, then by etching, leaving behind the insulating material on the edges of the window. The insulating material is preferably identical to the material forming the upper stop layer. Etching removes the upper stop layer situated in the bottom and at the center of the emitter window. Dry etching is preferable.
In one embodiment of the invention, prior to the stage of forming the emitter region, the lower stop layer situated in the bottom and at the center of the emitter window is etched selectively with respect to the heterojunction semiconducting layer so as to clear the heterojunction semiconducting layer.
In another embodiment of the invention, a layer of doped polysilicon is deposited in order to form an emitter region.
In still another embodiment of the invention, the layer of polysilicon is deposited non-selectively, followed by the layer of polysilicon. The upper insulating layer is etched anisotropically.
Advantageously, the polysilicon layer is of n+ type conductivity.
In one embodiment of the invention, the polysilicon layer is doped with arsenic.
Subsequently to the stage of forming the emitter region, the present invention makes it possible to remove by etching the polysilicon layer and the heterojunction semiconducting layer outside the active region and from a part of the insulating region surrounding the active region. It is possible to remove the lower insulating layer likewise outside the active region and from a part of the insulating region surrounding the active region.
An annealing is carried out in order to activate the implanted species. Spacers can be formed on the edges of the polysilicon layer and the heterojunction semiconducting layer and on the edges of the lower insulating layer, for example by depositing a supplementary insulating layer and isotropic etching. A metallic layer is deposited, comprising titanium for example, on the surface of the polysilicon layer and of the emitter region in order to ensure a high-quality electrical contact.
The invention likewise provides a bipolar transistor of the double-polysilicon, heterojunction-base type, comprising an active region of a semiconducting substrate and an insulating region surrounding the active region, an epitaxially grown silicon/germanium heterojunction semiconducting layer arranged on the active region and a part of the insulating region, at least one etching stop layer arranged on the heterojunction semiconducting layer above a part of the active region, a polysilicon layer arranged on the heterojunction semiconducting layer and on a part of the stop layer and an upper insulating layer on a part of the polysilicon layer, the upper insulating layer and the polysilicon layer leaving free an emitter window, spacers arranged in the emitter window, and an epitaxially grown emitter region arranged in the emitter window, resting partially on the upper insulating layer and in contact with the heterojunction semiconducting layer.
The active region of the substrate may comprise n+ and p+ type buried layers, an epitaxially grown collector of n type, and the insulating region can be formed by the shallow-trench method, known as STI (Shallow Trench Isolation).
In one embodiment of the invention, the transistor comprises a lower insulating layer partly covering the insulating region surrounding the active region while being provided with an aperture above the active region and a part of the insulating region.
The insulating region is preferably silicon oxide, silicon oxide nitride and/or amorphous silicon.
The silicon/germanium heterojunction semiconducting layer is preferably in direct contact with the active region.
In one embodiment of the invention, the transistor comprises a lower stop layer and an upper stop layer with compositions such that the stop layers can be etched selectively.
The lower stop layer may comprise silicon oxide and the upper stop layer may comprise silicon nitride. The stop layers are formed by deposition then etching. It is then possible to clean the upper surface of the heterojunction semiconducting layer in order to remove from it any traces of oxide, for example with hydrofluoric acid.
The polysilicon layer comprises a doping species in order to confer on it conductivity of p+ type. The polysilicon layer can be doped with boron. The upper insulating layer may comprise silicon oxide.
In one embodiment of the invention, the spacers comprise the same material as the upper stop layer.
In one embodiment of the invention, the emitter region comprises a doping species of n+ type conductivity. In one embodiment of the invention, the polysilicon layer is doped with arsenic.